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(parent: b56747a) | patch
drm/i915: Program correct m n tu register for Valleyview
authorVijay Purushothaman <vijay.a.purushothaman@intel.com>
Thu, 27 Sep 2012 13:43:04 +0000 (19:13 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 28 Sep 2012 14:49:53 +0000 (16:49 +0200)
commit74a4dd2e4594804ffeb04b3e60ff4cfbf6b8ce10
tree5b15df8a3458116a8111f4913d8eb4a9826e8078tree | snapshot
parentb56747aace48a269fefa7d337963cbae6e95b0a0commit | diff
drm/i915: Program correct m n tu register for Valleyview

m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c diff | blob | history
drivers/gpu/drm/i915/intel_dp.c diff | blob | history
John Crispins staging tree