perf, x86: Store perfctr msr addresses in config_base/event_base
authorRobert Richter <robert.richter@amd.com>
Wed, 2 Feb 2011 16:40:59 +0000 (17:40 +0100)
committerIngo Molnar <mingo@elte.hu>
Wed, 16 Feb 2011 12:30:52 +0000 (13:30 +0100)
commit73d6e52206a20354738418625cedc244cbfd5023
treed09c58e5cbf770e7d33c77b251326c975e17fb16
parent69d8e1e8ac0a7d829f1c0fd5bd07eb3022d9a1a0
perf, x86: Store perfctr msr addresses in config_base/event_base

Instead of storing the base addresses we can store the counter's msr
addresses directly in config_base/event_base of struct hw_perf_event.
This avoids recalculating the address with each msr access. The
addresses are configured one time. We also need this change to later
modify the address calculation.

Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <1296664860-10886-5-git-send-email-robert.richter@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/perf_event.c
arch/x86/kernel/cpu/perf_event_p4.c
arch/x86/kernel/cpu/perf_event_p6.c