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(parent: f073cd8) | patch
clk: qcom: msm8960: fix ce3_core clk enable register
authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Mon, 22 Feb 2016 11:43:39 +0000 (11:43 +0000)
committerStephen Boyd <sboyd@codeaurora.org>
Mon, 22 Feb 2016 22:15:53 +0000 (14:15 -0800)
commit732d6913691848db9fabaa6a25b4d6fad10ddccf
tree709e8daa51429f280679614510cffa4dd4b8013atree | snapshot
parentf073cd8a3e7b3b7d5f572b8178aa4abe6115e52fcommit | diff
clk: qcom: msm8960: fix ce3_core clk enable register

This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/qcom/gcc-msm8960.c diff | blob | history
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