drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
authorMichel Dänzer <michel.daenzer@amd.com>
Thu, 31 Jul 2014 09:43:49 +0000 (18:43 +0900)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 5 Aug 2014 12:53:45 +0000 (08:53 -0400)
commit72a9987edcedb89db988079a03c9b9c65b6ec9ac
tree80fb28570b7cf060188bdad013f0aa58b4a25fb0
parent124764f17473479061942429ada2e5e786d5d6ed
drm/radeon: Always flush the HDP cache before submitting a CS to the GPU

This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:

* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
  is performed via MMIO

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/cik.c
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_asic.h
drivers/gpu/drm/radeon/radeon_drv.c
drivers/gpu/drm/radeon/radeon_ring.c