perf/x86: Don't assume there can be only 4 PEBS events
authorAndi Kleen <ak@linux.intel.com>
Wed, 6 Jun 2012 00:56:48 +0000 (17:56 -0700)
committerIngo Molnar <mingo@kernel.org>
Wed, 6 Jun 2012 15:23:40 +0000 (17:23 +0200)
commit70ab7003dec58afeae7f5d681dfa309b3a259f03
treefe2a7fad09874b1a8bbe1c6793594996f1987be2
parentc48b60538c3ba05a7a2713c4791b25405525431b
perf/x86: Don't assume there can be only 4 PEBS events

On Sandy Bridge in non HT mode there are 8 counters available.
Since every counter can write a PEBS record assuming there are
4 max is incorrect. Use the reported counter number -- with an
upper limit for a static array -- instead.

Also I made the warning messages a bit more informational.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1338944211-28275-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/kernel/cpu/perf_event.h
arch/x86/kernel/cpu/perf_event_intel.c
arch/x86/kernel/cpu/perf_event_intel_ds.c