drm/amd/display: fix surface update sequence
authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Mon, 19 Nov 2018 21:25:23 +0000 (16:25 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 18 Dec 2018 23:25:11 +0000 (18:25 -0500)
commit6fd3583b92318d6d8367cc3f325a81a222cdbc55
treec2304ea1e4dd0b1a43368eabc05178c644732006
parent12750d1647f118496f1da727146f255f5e44d500
drm/amd/display: fix surface update sequence

An earlier change added update of interdependent dlg/ttu params for pipes
not being updated in the current call. The code fails to check if the other
pipes are actually active yet causing an assert.

This change adds a check for surface presence on the pipes before updating
the interdepenednt params.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c