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(parent: aea17f9) | patch
Fix two bugs for MPC83xx DDR2 controller SPD Init
authorXie Xiaobo <r63061@freescale.com>
Fri, 9 Mar 2007 11:08:25 +0000 (19:08 +0800)
committerKim Phillips <kim.phillips@freescale.com>
Thu, 12 Apr 2007 22:39:03 +0000 (17:39 -0500)
commit6fbf261f8df294e589cfadebebe5468e3c0f29e9
tree592fb707b77e2a37a5259119149566192a7d7e49tree | snapshot
parentaea17f99278818caa327ad0e511b48d1761fb10ccommit | diff
Fix two bugs for MPC83xx DDR2 controller SPD Init

There are a few bugs in the cpu/mpc83xx/spd_sdram.c
the first bug is that the picos_to_clk routine introduces a huge
rounding error in 83xx.
the second bug is that the mode register write recovery field is
tWR-1, not tWR >> 1.
cpu/mpc83xx/spd_sdram.c diff | blob | history
Broadcom-s U-Boot