dmaengine: xilinx_dma: Fix 64-bit simple AXIDMA transfer
authorRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Thu, 26 Sep 2019 10:50:57 +0000 (16:20 +0530)
committerVinod Koul <vkoul@kernel.org>
Tue, 15 Oct 2019 10:11:55 +0000 (15:41 +0530)
commit68fe2b520cee829ed518b4b1f64d2a557bcbffe1
tree6cbe57e6d548617343d316b84a45c1e5601c067b
parentbd73dfabdda280fc5f05bdec79b6721b4b2f035f
dmaengine: xilinx_dma: Fix 64-bit simple AXIDMA transfer

In AXI DMA simple mode also pass MSB bits of source and destination
address to xilinx_write function. It fixes simple AXI DMA operation
mode using 64-bit addressing.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Link: https://lore.kernel.org/r/1569495060-18117-2-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/dma/xilinx/xilinx_dma.c