projects / openwrt / staging / xback.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 285f87d) | patch
ramips: add back the missing periph clock for Ralink RT3883
authorShiji Yang <yangshiji66@qq.com>
Tue, 6 Aug 2024 12:52:55 +0000 (20:52 +0800)
committerHauke Mehrtens <hauke@hauke-m.de>
Sun, 22 Sep 2024 17:12:16 +0000 (19:12 +0200)
commit656c9847d51d4d2675c94027804e79fc5d8a257b
treeec282b571c712ffc01ee125ed8f05e509cd0376etree | snapshot
parent285f87d2c73c9c84f7316efd89a3987c3011ff12commit | diff
ramips: add back the missing periph clock for Ralink RT3883

periph clock is the parent clock of some other clocks.

Link: https://lore.kernel.org/all/CAMhs-H_NS-n2tx5SZpCMiVZtBFzX_nTa_vnS8We0UevkwFq93Q@mail.gmail.com/
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Link: https://github.com/openwrt/openwrt/pull/16318
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
target/linux/ramips/dts/rt3883.dtsi diff | blob | history
target/linux/ramips/patches-6.6/100-clk-ralink-mtmips-fix-clock-plan-for-Ralink-SoC-RT3883.patch [new file with mode: 0644] blob
Staging tree of Koen Vandeputte