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(parent: 77b0532) | patch
GICv3: Allow either G1S or G0 interrupts to be configured
authorYatharth Kochar <yatharth.kochar@arm.com>
Tue, 6 Sep 2016 10:48:05 +0000 (11:48 +0100)
committerYatharth Kochar <yatharth.kochar@arm.com>
Mon, 12 Sep 2016 15:19:08 +0000 (16:19 +0100)
commit6083c841d0c43f2136921156abef7b684dce7bf0
treeb9f3e85461c9a5ded71e56de658dbb8990302d13tree | snapshot
parent77b05323921c23e4261ddd8fee5c326a79b0af97commit | diff
GICv3: Allow either G1S or G0 interrupts to be configured

Currently the GICv3 driver mandates that platform populate
both G1S and G0 interrupts. However, it is possible that a
given platform is not interested in both the groups and
just needs to specify either one of them.

This patch modifies the `gicv3_rdistif_init()` & `gicv3_distif_init()`
functions to allow either G1S or G0 interrupts to be configured.

Fixes ARM-software/tf-issues#400

Change-Id: I43572b0e08ae30bed5af9334f25d35bf439b0d2b
drivers/arm/gic/v3/gicv3_main.c diff | blob | history
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