drm/i915: drop buggy write to FDI_RX_CHICKEN register
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 14 Nov 2012 16:47:39 +0000 (17:47 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 21 Nov 2012 16:45:01 +0000 (17:45 +0100)
commit607a6f7a6621f65706ff536b2615ee65b5c2f575
treedeee241803e18c10db7e0c56a77ad2bfd17fb138
parent1c8b46fc8c865189f562c9ab163d63863759712f
drm/i915: drop buggy write to FDI_RX_CHICKEN register

Jani Nikula noticed that the parentheses are wrong and we & the bit
with the register address instead of the read-back value. He sent a
patch to correct that.

On second look, we write the same register in the previous line, and
the w/a seems to be to set FDI_RX_PHASE_SYNC_POINTER_OVR to enable the
logic, then keep always set FDI_RX_PHASE_SYNC_POINTER_OVR and toggle
FDI_RX_PHASE_SYNC_POINTER_EN before/after enabling the pc transcoder.

So the right things seems to be to simply kill the 2nd write.

Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Dropped a bogus ~ from the commit message that somehow crept
in.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c