net: hns3: Fix for phy link issue when using marvell phy driver
authorJian Shen <shenjian15@huawei.com>
Tue, 14 Aug 2018 16:13:15 +0000 (17:13 +0100)
committerDavid S. Miller <davem@davemloft.net>
Tue, 14 Aug 2018 16:54:23 +0000 (09:54 -0700)
commit60081dcc4fce385ade26d3145b2479789df0b7e5
tree723d59fd8f96f7307c83c494e646b3c1f1a574be
parentb01b7cf19bf4a677d5dd4e63b12d86a021db751d
net: hns3: Fix for phy link issue when using marvell phy driver

For marvell phy m88e1510, bit SUPPORTED_FIBRE of phydev->supported
is default on. Both phy_resume() and phy_suspend() will check the
SUPPORTED_FIBRE bit and write register of fibre page.

Currently in hns3 driver, the SUPPORTED_FIBRE bit will be cleared
after phy_connect_direct() finished. Because phy_resume() is called
in phy_connect_direct(), and phy_suspend() is called when disconnect
phy device, so the operation for fibre page register is not symmetrical.
It will cause phy link issue when reload hns3 driver.

This patch fixes it by disable the SUPPORTED_FIBRE before connecting
phy.

Fixes: 256727da7395 ("net: hns3: Add MDIO support to HNS3 Ethernet driver for hip08 SoC")
Signed-off-by: Jian Shen <shenjian15@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c