projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 6be5ed3) | patch
gianfar: Remove redundant programming of [rt]xic registers
authorClaudiu Manoil <claudiu.manoil@freescale.com>
Tue, 19 Mar 2013 07:40:04 +0000 (07:40 +0000)
committerDavid S. Miller <davem@davemloft.net>
Wed, 20 Mar 2013 17:21:52 +0000 (13:21 -0400)
commit5d9657d83a1cfecfbe41add0d94863d3fe714df0
tree4c51232b94ee418c4021c65d4de8008c5b14be7dtree | snapshot
parent6be5ed3fef568ad79f9519db4a336c725a089d51commit | diff
gianfar: Remove redundant programming of [rt]xic registers

For Multi Q Multi Group (MQ_MG_MODE) mode, the Rx/Tx colescing registers [rt]xic
are aliased with the [rt]xic0 registers (coalescing setting regs for Q0). This
avoids programming twice in a row the coalescing registers for the Rx/Tx hw Q0.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/freescale/gianfar.c diff | blob | history
John Crispins staging tree