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(parent: a5eb04d) | patch
x86: Allow timer calibration to work on ivybridge
authorSimon Glass <sjg@chromium.org>
Thu, 13 Nov 2014 05:42:04 +0000 (22:42 -0700)
committerSimon Glass <sjg@chromium.org>
Fri, 21 Nov 2014 06:24:12 +0000 (07:24 +0100)
commit5c1b685e46756dc9504b919336321dad27dbcd9e
treee4a3f61e5571d16f283863f6ca29e30f5a819a53tree | snapshot
parenta5eb04db1a8fac8c7691c87cbbb890c8174ab906commit | diff
x86: Allow timer calibration to work on ivybridge

Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method
seems to take up to 50ms which is much too long.

For this CPU we know the frequency, so add another special case for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
arch/x86/lib/tsc_timer.c diff | blob | history
Broadcom-s U-Boot