drm/i915: align vlv forcewake with common lore
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 24 Aug 2012 15:26:20 +0000 (17:26 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 3 Sep 2012 08:09:28 +0000 (10:09 +0200)
commit5ab140a4ac08c895b67c2755e6f988ea92b5818b
tree5b21f68b6c31ba6bfc13188c5f80fb9549e71c86
parentbe2cde9a6d922e5e43efd2ad39bc43ce70a5d79b
drm/i915: align vlv forcewake with common lore

For some odd reasons, the vlv forcewake code is rather different from
all other platforms, with no clear justification. Adjust things:

- Don't check whether the gt is awake already (and bail out early), we
  need to grab a forcewake anyway. Otherwise the chip might go to
  sleep too early. And this would also screw up our forcewake
  accounting.
- Like all other platforms, check whether the gt has cleared the
  forcewake bit in the _ACK register before setting it again.
- Use _MASKED_BIT_ENABLE/DISABLE macros
- Only use bit0 of the forcewake reg, not all 16 bits.
- check the gtfifodb reg like on all other platforms in _put.
- Drop the POSTING_READs for consistency.

v2: Failure to git add ... again.

v3: Fixup the spelling fail a bit.

Tested-by: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Tested-by: "Widawsky, Benjamin" <benjamin.widawsky@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c