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(parent: 100edfe) | patch
clk: cdce925: Fix limit check
authorChristophe JAILLET <christophe.jaillet@wanadoo.fr>
Fri, 11 Nov 2016 21:49:05 +0000 (22:49 +0100)
committerStephen Boyd <sboyd@codeaurora.org>
Fri, 9 Dec 2016 00:29:36 +0000 (16:29 -0800)
commit5785271ef2bb9ca37ba1b40ec56b8d127caf3b2c
tree6c908df249f189f86c7045a8dd3eeccb1f067abetree | snapshot
parent100edfe33a313f2d076a5edf4b105eeb6137ab9acommit | diff
clk: cdce925: Fix limit check

It is likely that instead of '1>64', 'q>64' was expected.

Moreover, according to datasheet,
   http://www.ti.com/lit/ds/symlink/cdce925.pdf
   SCAS847I - JULY 2007 - REVISED OCTOBER 2016
PLL settings limits are: 16 <= q <= 63
So change the upper limit check from 64 to 63.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/clk-cdce925.c diff | blob | history
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