drm/i915/skl+: Decode memory bandwidth and parameters
authorMahesh Kumar <mahesh1.kumar@intel.com>
Fri, 24 Aug 2018 09:32:22 +0000 (15:02 +0530)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 13 Sep 2018 21:33:03 +0000 (14:33 -0700)
commit5771caf885ae779ade0ea009ae5d5f363bb72a52
tree627ec814319750012c3c62ec0eb2d489dab24645
parentcbfa59d4b331046d89c795c8e809922f345d9bd7
drm/i915/skl+: Decode memory bandwidth and parameters

This patch adds support to decode system memory bandwidth and other
parameters for skylake and Gen9+ platforms, which will be used for
arbitrated display memory bandwidth calculation in GEN9 based
platforms and WM latency level-0 Work-around calculation on GEN9+.

Changes Since V1:
 - s/memdev_info/dram_info
 - create a struct to hold channel info
Changes Since V2:
 - rewrite code to adhere i915 coding style
 - not valid for GLK

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180824093225.12598-3-mahesh1.kumar@intel.com
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_reg.h