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ath79: ag71xx: fix pll-data setting for ar7242/ar934x/qca955x/qca956x
authorWeijie Gao <hackpascal@gmail.com>
Wed, 13 Jun 2018 13:41:59 +0000 (21:41 +0800)
committerJohn Crispin <john@phrozen.org>
Mon, 18 Jun 2018 16:21:19 +0000 (18:21 +0200)
commit52109ce71f3d864775fda04284d02425b96378d8
tree3534480bc22a50dcea621770d2b22b59e368f352tree | snapshot
parent97c5cbc496e9cf8139994cd3ea987f4e9c70adbecommit | diff
ath79: ag71xx: fix pll-data setting for ar7242/ar934x/qca955x/qca956x

ar71xx/ar913x series use the old pll registers and settings.

However started from ar7242, a new pll register is introduced and the
pll setting is much simpler.

This can be observed from dev-eth.c from the ar71xx target.

Signed-off-by: Weijie Gao <hackpascal@gmail.com>
target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c diff | blob | history
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