Add workaround for errata 1130799 for Cortex-A76
authorLouis Mayencourt <louis.mayencourt@arm.com>
Thu, 21 Feb 2019 17:35:07 +0000 (17:35 +0000)
committerLouis Mayencourt <louis.mayencourt@arm.com>
Tue, 26 Feb 2019 16:21:06 +0000 (16:21 +0000)
commit508d71108a06c7fce2eeef78659b9b7739cee6eb
tree0a79684da2ea12a62188da7d4415598f2a0d4398
parent98551591f5371de2c2f0dee6be2e12b75653f04d
Add workaround for errata 1130799 for Cortex-A76

TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.

Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
docs/cpu-specific-build-macros.rst
lib/cpus/aarch64/cortex_a76.S
lib/cpus/cpu-ops.mk