Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock
authorJoe D'Abbraccio <ljd015@freescale.com>
Mon, 24 Mar 2008 17:00:59 +0000 (13:00 -0400)
committerKim Phillips <kim.phillips@freescale.com>
Wed, 26 Mar 2008 00:16:48 +0000 (19:16 -0500)
commit507e2d79c91441a0bb2cd3d0c31c8bfe3f8cec07
tree387333d74f0a89108de998422da7c5efb4c5ea91
parenta7ba32d480a86db5db8dcd8ca66b21b4cadda923
Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock

With the original value of 1/2 clock cycle delay, the system ran relatively
stable except when we run benchmarks that are intensive users of memory.
When I run samba connected disk with a HDBENCH test, the system locks-up
or reboots sporadically.

Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
include/configs/MPC8349ITX.h