projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 1001354) | patch
clk: renesas: Add r8a7743 CPG Core Clock Definitions
authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thu, 27 Oct 2016 20:23:35 +0000 (23:23 +0300)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 7 Nov 2016 14:09:12 +0000 (15:09 +0100)
commit4e195933de4690c503ce4b93cfd0fb0046dd770b
tree767c005d675dd2f9b374b48a6a2a343e5e493d51tree | snapshot
parent1001354ca34179f3db924eb66672442a173147dccommit | diff
clk: renesas: Add r8a7743 CPG Core Clock Definitions

Add macros usable by the device tree sources to reference the R8A7743 CPG
clocks by index. The data comes from Table 7.2b in revision 1.00 of the
RZ/G Series User's Manual.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
include/dt-bindings/clock/r8a7743-cpg-mssr.h [new file with mode: 0644] blob
John Crispins staging tree