projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 54ecb8f) | patch
clk: mvebu: armada-37xx-periph: add PCIe gated clock
authorMiquel Raynal <miquel.raynal@bootlin.com>
Thu, 27 Jun 2019 12:52:42 +0000 (14:52 +0200)
committerStephen Boyd <sboyd@kernel.org>
Thu, 3 Oct 2019 21:00:20 +0000 (14:00 -0700)
commit4d8fb4948472c976d0c6dcf3380f92332dd660c1
treed06593bfe388c37f793d0b36f8e2680729046702tree | snapshot
parent54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5ccommit | diff
clk: mvebu: armada-37xx-periph: add PCIe gated clock

The PCIe clock is a gated clock which has the same source as GbE0
(both IPs share a set of registers). This source clock is called
'gbe_core' in the driver.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190627125245.26788-2-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/mvebu/armada-37xx-periph.c diff | blob | history
John Crispins staging tree