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(parent: f0aa26f) | patch
lpc32xx: fix calculation of HCLK PLL output clock
authorVladimir Zapolskiy <vz@mleia.com>
Sun, 4 Oct 2015 22:18:45 +0000 (23:18 +0100)
committerTom Rini <trini@konsulko.com>
Sun, 11 Oct 2015 21:12:13 +0000 (17:12 -0400)
commit4c90234586833c0bb4a5d9d3f69a69c8ab09e01f
tree2ac2373905fe23b18d4c4eddc897de6664bc842btree | snapshot
parentf0aa26f006339969d5e712c50fdb6838333be3b8commit | diff
lpc32xx: fix calculation of HCLK PLL output clock

Execution branches on feedback mode are swapped, this has no effect
if default direct mode is on (then p_div is equal to 1 and Fout equals
to Fcco), that's why the problem remained unnoticed for a long time.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
arch/arm/cpu/arm926ejs/lpc32xx/clk.c diff | blob | history
Broadcom-s U-Boot