IB/mlx5: Fix cached MR allocation flow
authorMajd Dibbiny <majd@mellanox.com>
Mon, 12 Jun 2017 07:36:15 +0000 (10:36 +0300)
committerDoug Ledford <dledford@redhat.com>
Mon, 24 Jul 2017 14:41:01 +0000 (10:41 -0400)
commit4c25b7a39005c9243a492b577c3e940eeac36a25
tree1400341f8aea65b275d36711c5798257b82c3253
parent1d54f89094e2d2067948550ec52aab93e15b4b0c
IB/mlx5: Fix cached MR allocation flow

When we have a miss in one order of the mkey cache, we try to get
an mkey from a higher order.

We still need to check that the higher order can be used with UMR
before using it. Otherwise, we will get an mkey with 0 entries and
the post send operation that is used to fill it will complete with
the following error:

mlx5_0:dump_cqe:275:(pid 0): dump error cqe
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 0f007806 25000025 49ce59d2

Fixes: 49780d42dfc9 ("IB/mlx5: Expose MR cache for mlx5_ib")
Cc: <stable@vger.kernel.org> # v4.10+
Signed-off-by: Majd Dibbiny <majd@mellanox.com>
Reviewed-by: Ilya Lesokhin <ilyal@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Doug Ledford <dledford@redhat.com>
drivers/infiniband/hw/mlx5/mr.c