board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M
authorStephen George <stephen.george@freescale.com>
Mon, 25 Mar 2013 07:40:12 +0000 (07:40 +0000)
committerAndy Fleming <afleming@freescale.com>
Fri, 24 May 2013 21:54:12 +0000 (16:54 -0500)
commit49e946cb6ae0448492147ffcb9dcd7d0af1eab4d
tree07118135410c7b399c8ac780b6fa803ceebdfaea
parent94025b1cd8d9959ebf987a7f6382d513c606ecf1
board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M

Debug trace buffers are memory mapped in DCSR space beyond 4M.

Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
board/freescale/b4860qds/law.c
board/freescale/b4860qds/tlb.c
board/freescale/t4qds/law.c
board/freescale/t4qds/tlb.c
doc/README.b4860qds
doc/README.t4240qds