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ti: k3: common: Remove coherency workaround for AM65x
authorAndrew F. Davis <afd@ti.com>
Thu, 25 Apr 2019 18:33:30 +0000 (14:33 -0400)
committerJohn Tsichritzis <john.tsichritzis@arm.com>
Thu, 6 Jun 2019 10:20:26 +0000 (11:20 +0100)
commit48d6b2643462b43ed617ca3751121a5587881e44
tree351d6dc998168666a4d8211372834e523e7d7f26tree | snapshot
parent65f7b81728d0701e93bd13cee4e88375ec9e9b17commit | diff
ti: k3: common: Remove coherency workaround for AM65x

We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the last accessed areas all being marked as non-cached by
USE_COHERENT_MEM we can rely on that to workaround our interconnect
issues. Remove the old workaround.

Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7
Signed-off-by: Andrew F. Davis <afd@ti.com>
lib/cpus/aarch64/cortex_a53.S diff | blob | history
plat/ti/k3/common/k3_psci.c diff | blob | history
plat/ti/k3/common/plat_common.mk diff | blob | history
Broadcom-s Trusted Firmware A