drm/amd/display: Set disp clk in a safe way to avoid over high dpp clk. (v2)
authorYongqiang Sun <yongqiang.sun@amd.com>
Wed, 28 Feb 2018 22:14:50 +0000 (17:14 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 14 Mar 2018 20:16:34 +0000 (15:16 -0500)
commit45bb8dd696eaff9c96afd2b210f0d8cf5025dd65
treeda8602a53412e46bf5f0555f038503dac4269b47
parent5231f5d1124eef853573cb3d2e3dc3c4ddc43e22
drm/amd/display: Set disp clk in a safe way to avoid over high dpp clk. (v2)

Increase clock, if current dpp div is 0 and request dpp div is 1, request clk is
higher than maximum dpp clk as per dpm table.
set dispclk to the value of maximum supported dpp clk
set div to 1
set dispclk to request value.
Decrease clock, currrent dpp div is 1 and request dpp div is 0, current clk is
higher than maximum dpp clk as per dpm table.
set dispclk to the value of maximum supported dpp clk
set div to 0
set dispclk to request value.

v2: squash in !DCN build fix

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
drivers/gpu/drm/amd/display/dc/dc.h
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c