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[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 5
authorChris Zankel <czankel@tensilica.com>
Fri, 24 Jun 2005 05:01:24 +0000 (22:01 -0700)
committerLinus Torvalds <torvalds@ppc970.osdl.org>
Fri, 24 Jun 2005 07:05:22 +0000 (00:05 -0700)
commit3f65ce4d141e435e54c20ed2379d983d362a2cb5
tree1e86807b3f215d90d9cf57aa609f73f856515b30tree | snapshot
parent249ac17e96811acc3c6402317dd5d5c89d2cbf68commit | diff
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 5

The attached patches provides part 5 of an architecture implementation for the
Tensilica Xtensa CPU series.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
arch/xtensa/mm/Makefile [new file with mode: 0644] blob
arch/xtensa/mm/fault.c [new file with mode: 0644] blob
arch/xtensa/mm/init.c [new file with mode: 0644] blob
arch/xtensa/mm/misc.S [new file with mode: 0644] blob
arch/xtensa/mm/pgtable.c [new file with mode: 0644] blob
arch/xtensa/mm/tlb.c [new file with mode: 0644] blob
John Crispins staging tree