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(parent: 85a02de) | patch
drm/i915: MCH_SSKPD is a 64 bit register on Haswell
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Fri, 3 May 2013 20:23:44 +0000 (17:23 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 21 May 2013 10:00:26 +0000 (12:00 +0200)
commit3e1f72664e0a8a31e9b90c48459deb6642fd52f3
treecf20d09a07accd98b0e81f94072b9e7fd8c737bbtree | snapshot
parent85a02deb4ca5a7e1e39e8538b6eb3c7066469720commit | diff
drm/i915: MCH_SSKPD is a 64 bit register on Haswell

And the SNB_READ_WM0_LATENCY macro is not valid anymore because we
have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if
the new one is not zero.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c diff | blob | history
John Crispins staging tree