drm/i915/gen7: Re-enable full-ppgtt for ivb & hsw
authorChris Wilson <chris@chris-wilson.co.uk>
Fri, 29 Nov 2019 20:13:28 +0000 (20:13 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Sat, 30 Nov 2019 09:21:12 +0000 (09:21 +0000)
commit3cd6e8860ecd40f358b9d30d5bfecbc74fd7cfef
tree661769d0f711b9d18ccdc2c33539a9bf40f8fdc8
parentf9a863c2ffc17f72137fae8cac3314961dc6be24
drm/i915/gen7: Re-enable full-ppgtt for ivb & hsw

After much hair pulling, resort to preallocating the ppGTT entries on
init to circumvent the apparent lack of PD invalidate following the
write to PP_DCLV upon switching mm between contexts (and here the same
context after binding new objects). However, the details of that PP_DCLV
invalidate are still unknown, and it appears we need to reload the mm
twice to cover over a timing issue. Worrying.

Fixes: 3dc007fe9b2b ("drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgtt")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191129201328.1398583-1-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/gt/intel_ring_submission.c
drivers/gpu/drm/i915/i915_gem_gtt.c
drivers/gpu/drm/i915/i915_gem_gtt.h
drivers/gpu/drm/i915/i915_pci.c