spl: fit: display a message when an FPGA image is loaded
authorLuis Araneda <luaraneda@gmail.com>
Thu, 19 Jul 2018 07:10:16 +0000 (03:10 -0400)
committerMichal Simek <michal.simek@xilinx.com>
Thu, 19 Jul 2018 08:49:56 +0000 (10:49 +0200)
commit3907eef1a385e52d99d9888de078cd652548a668
treef3e3f86320fd86aec650a419ea6d0bd733d0193a
parenta133b3ac3257e471f521991e472c8f8c15d2c5a9
spl: fit: display a message when an FPGA image is loaded

A message should be displayed if an image is loaded
to an FPGA, because the hardware might have changed,
and the user should be informed

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
common/spl/spl_fit.c