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(parent: 6e3732a) | patch
clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits
authorXing Zheng <zhengxing@rock-chips.com>
Thu, 30 Jun 2016 02:18:59 +0000 (10:18 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Thu, 30 Jun 2016 23:50:17 +0000 (01:50 +0200)
commit3770821fa360525e6c726cd562a2438a0aa5d566
treeec494e523c723b6a1adbe00d46b2584c3321a897tree | snapshot
parent6e3732a2bebc3f08a59d2eafc2aa613b92055e3fcommit | diff
clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits

The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
it should be bit_8, let's fix it.

Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399")
Reported-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3399.c diff | blob | history
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