projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: c175e7a) | patch
ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node
authorGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 23 Nov 2015 13:55:59 +0000 (14:55 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Wed, 25 Nov 2015 01:42:19 +0000 (10:42 +0900)
commit374e70075e58acfe922869aad1202b29f8fb76f5
treef0e465742b211a83e6a4c3eb96f58524207319a3tree | snapshot
parentc175e7abf75f174a781d1218aa6fb2bdf2ff3eaecommit | diff
ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node

Add the missing L2 cache-controller node, and link the CPU node to it.
This will allow migration to the generic l2c OF initialization.

The L2 cache is an ARM L2C-310 (r3p1-150rel0), of size 256 KiB (32 KiB x
8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7740.dtsi diff | blob | history
John Crispins staging tree