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(parent: 3b25b76) | patch
MIPS: Decode config3 register on Ingenic SoCs
authorPaul Cercueil <paul@crapouillou.net>
Tue, 7 May 2019 22:43:57 +0000 (00:43 +0200)
committerPaul Burton <paul.burton@mips.com>
Sun, 21 Jul 2019 22:23:24 +0000 (15:23 -0700)
commit368fb26c1e55a187131a794f95420d96d31d0e5e
treefa730e4917d920e082f2b1de4f50947b2787beddtree | snapshot
parent3b25b763116482596227225bea7c03fcde11c9edcommit | diff
MIPS: Decode config3 register on Ingenic SoCs

XBurst misses a config2 register, so config3 decode was skipped in
decode_configs().

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: od@zcrc.me
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
arch/mips/kernel/cpu-probe.c diff | blob | history
John Crispins staging tree