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(parent: 4c4a39d) | patch
arm64: Handle mismatched cache type
authorSuzuki K Poulose <suzuki.poulose@arm.com>
Wed, 4 Jul 2018 22:07:46 +0000 (23:07 +0100)
committerWill Deacon <will.deacon@arm.com>
Thu, 5 Jul 2018 09:20:59 +0000 (10:20 +0100)
commit314d53d297980676011e6fd83dac60db4a01dc70
tree201eddf7774afbd9ef20845a69f091aeef94e056tree | snapshot
parent4c4a39dd5fe2d13e2d2fa5fceb8ef95d19fc389acommit | diff
arm64: Handle mismatched cache type

Track mismatches in the cache type register (CTR_EL0), other
than the D/I min line sizes and trap user accesses if there are any.

Fixes: be68a8aaf925 ("arm64: cpufeature: Fix CTR_EL0 field definitions")
Cc: <stable@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
arch/arm64/include/asm/cpucaps.h diff | blob | history
arch/arm64/kernel/cpu_errata.c diff | blob | history
John Crispins staging tree