ravb: do not write 1 to reserved bits
authorKazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Tue, 18 Sep 2018 10:22:26 +0000 (12:22 +0200)
committerDavid S. Miller <davem@davemloft.net>
Wed, 19 Sep 2018 03:09:57 +0000 (20:09 -0700)
commit2fe397a3959de8a472f165e6d152f64cb77fa2cc
tree3e8953c631443845a823646b5a38257ee8b48d87
parent65fac4fe9080714df80d430888834ce87c6716ba
ravb: do not write 1 to reserved bits

EtherAVB hardware requires 0 to be written to status register bits in
order to clear them, however, care must be taken not to:

1. Clear other bits, by writing zero to them
2. Write one to reserved bits

This patch corrects the ravb driver with respect to the second point above.
This is done by defining reserved bit masks for the affected registers and,
after auditing the code, ensure all sites that may write a one to a
reserved bit use are suitably masked.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/renesas/ravb.h
drivers/net/ethernet/renesas/ravb_main.c
drivers/net/ethernet/renesas/ravb_ptp.c