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(parent: 8f33a15) | patch
drm/radeon/hdmi: DCE3: clean ACR control
authorRafał Miłecki <zajec5@gmail.com>
Fri, 16 May 2014 09:10:29 +0000 (11:10 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 2 Jun 2014 14:25:04 +0000 (10:25 -0400)
commit2e93cac90c4b063c8732deb727a192dea1119640
treed693edcb5a2ae13673e194f2985bf8b417f1d2d3tree | snapshot
parent8f33a156c2adeddb5b5755b277b2c0b68da56ae2commit | diff
drm/radeon/hdmi: DCE3: clean ACR control

What initially seemed to be a typo in fglrx (using register 0x740c
instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and
CRC registers swapped which explains why we needed
WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);

This has been tested for possible regressions on DCE3 HD3470 (RV620).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/r600_hdmi.c diff | blob | history
drivers/gpu/drm/radeon/r600d.h diff | blob | history
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