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(parent: 42c9a85) | patch
lantiq: Fixed reading the number of RX FIFOs in the SPI driver
authorJohn Crispin <john@openwrt.org>
Mon, 19 Oct 2015 10:08:18 +0000 (10:08 +0000)
committerJohn Crispin <john@openwrt.org>
Mon, 19 Oct 2015 10:08:18 +0000 (10:08 +0000)
commit2c7d536780600242d804bca1383c896ccff350c4
tree014c507ad85917e83ea22f3f36fe136cc8e0ebf9tree | snapshot
parent42c9a85e8e81cead3188481d8ff571e2a326e46bcommit | diff
lantiq: Fixed reading the number of RX FIFOs in the SPI driver

Until now the SPI driver used the TX bits for the RX FIFO. This seems
uncritical for now since both are equals on my devices (VR9), but this
could cause problems on other SoCs.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 47208
target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch diff | blob | history
target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch diff | blob | history
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