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(parent: 28c2337) | patch
drm/tegra: sor: Registers are 32-bit
authorThierry Reding <treding@nvidia.com>
Mon, 26 Jan 2015 15:02:48 +0000 (16:02 +0100)
committerThierry Reding <treding@nvidia.com>
Thu, 2 Apr 2015 16:46:16 +0000 (18:46 +0200)
commit28fe2076004da062e9affac1cec98c697de53eb1
treed40639a99dc33d82b6586b2b27c68c36bac18d46tree | snapshot
parent28c23373b88bcc244b573ea45596a51e9db73d2ccommit | diff
drm/tegra: sor: Registers are 32-bit

Use a sized unsigned 32-bit data type (u32) to store register contents.
The SOR registers are 32 bits wide irrespective of the architecture's
data width.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/sor.c diff | blob | history
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