generic: MIPS: Add barriers between dcache & icache flushes
authorDavid Bauer <mail@david-bauer.net>
Thu, 2 Mar 2023 15:53:59 +0000 (16:53 +0100)
committerDavid Bauer <mail@david-bauer.net>
Sat, 4 Mar 2023 12:09:30 +0000 (13:09 +0100)
commit26bc8f68767e1ec6e33a84ef397e4c38d5968462
treeb7a4106fdbd50db854f3ebfb86855df842d7a198
parent0aedf916df364771be47ffda8ff3465250ecee77
generic: MIPS: Add barriers between dcache & icache flushes

This fixes spurious boot-errors with some ath79 MIPS 74Kc boards such
as the AC Lite as well as Archer C7 v2.

The missing barrier leads to the icache flush being executed before the
dcache writeback, which results in the CPU executing the dummy infinite
loop in tlbmiss_handler_setup_pgd.

Applying this patch from upstream ensures the dcache is written back
before flushing the icache.

Signed-off-by: David Bauer <mail@david-bauer.net>
target/linux/generic/pending-5.10/301-MIPS-Add-barriers-between-dcache-icache-flushes.patch [new file with mode: 0644]
target/linux/generic/pending-5.15/301-MIPS-Add-barriers-between-dcache-icache-flushes.patch [new file with mode: 0644]