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(parent: 3c251af) | patch
Enable data caches early with hardware-assisted coherency
authorJeenu Viswambharan <jeenu.viswambharan@arm.com>
Thu, 5 Jan 2017 10:37:21 +0000 (10:37 +0000)
committerJeenu Viswambharan <jeenu.viswambharan@arm.com>
Thu, 2 Mar 2017 11:00:20 +0000 (11:00 +0000)
commit25a93f7cd181ca79a631864b7c076fa7106f4365
tree0c78e4a1940cc16e9684cbd4f758d7b559f1da1ctree | snapshot
parent3c251af392f2dfeedfe9c4595a8a33188c1d1d14commit | diff
Enable data caches early with hardware-assisted coherency

At present, warm-booted CPUs keep their caches disabled when enabling
MMU, and remains so until they enter coherency later.

On systems with hardware-assisted coherency, for which
HW_ASSISTED_COHERENCY build flag would be enabled, warm-booted CPUs can
have both caches and MMU enabled at once.

Change-Id: Icb0adb026e01aecf34beadf49c88faa9dd368327
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
bl31/aarch64/bl31_entrypoint.S diff | blob | history
bl32/sp_min/aarch32/entrypoint.S diff | blob | history
Broadcom-s Trusted Firmware A