projects / openwrt / staging / ynezz.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 0c8d7e3) | patch
realtek: add PLL DT binding includes
authorMarkus Stockhausen <markus.stockhausen@gmx.de>
Wed, 24 Aug 2022 18:57:05 +0000 (20:57 +0200)
committerSander Vanheule <sander@svanheule.net>
Sun, 28 Aug 2022 09:03:34 +0000 (11:03 +0200)
commit1efaad03bb20e9aee458d30427cf00170fbe8fa2
tree866a5b7828bef935ce4de1e612590231ea24774atree | snapshot
parent0c8d7e34ab35f6b41f034fd94fec740970e0125bcommit | diff
realtek: add PLL DT binding includes

Add some constants for sharing between DT and drivers.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
target/linux/realtek/files-5.10/include/dt-bindings/clock/rtl83xx-clk.h [new file with mode: 0644] blob
Staging tree of Petr Stetiar