clk: xgene: Add PMD clock
authorHoan Tran <hotran@apm.com>
Mon, 12 Sep 2016 18:23:24 +0000 (11:23 -0700)
committerStephen Boyd <sboyd@codeaurora.org>
Wed, 14 Sep 2016 20:54:35 +0000 (13:54 -0700)
commit1a85b50bef13b44016c206272785a746adae7833
tree7495fc987a795c2132b11d88592e402a874cb634
parent405f27be6182362e343c25ae6ec2b2933919ef30
clk: xgene: Add PMD clock

Add X-Gene PMD clock support.

PMD clock is implemented for a single register field.
  Output rate = parent_rate * (denominator - scale) / denominator
with
  - denominator = bitmask of register field + 1
  - scale = values of register field

For example, for bitmask is 0x7, denominator will be 8 and scale
will be computed and programmed accordingly.

Signed-off-by: Hoan Tran <hotran@apm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/clk-xgene.c