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(parent: 00c09d7) | patch
drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpaths
authorMika Kuoppala <mika.kuoppala@linux.intel.com>
Mon, 29 Oct 2012 14:59:26 +0000 (16:59 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Sun, 11 Nov 2012 22:51:09 +0000 (23:51 +0100)
commit17f10fdc010254b8e9c0f1779abdaaee4757cabf
treedc514c52a0091c6212afd2a9d188e45f706c733ctree | snapshot
parent00c09d70df6b30c980f20facc1db3def3f5a637ecommit | diff
drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpaths

Make intel_render_ring_init_dri and intel_init_ring_buffer symmetrical
with regards of workaround introduced by:

commit 27c1cbd06a7620b354cbb363834f3bb8df4f410d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Apr 9 13:59:46 2012 +0100

    drm/i915/ringbuffer: Exclude last 2 cachlines of ring on 845g

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ringbuffer.c diff | blob | history
John Crispins staging tree