Initialise CPU contexts from entry_point_info
authorAndrew Thoelke <andrew.thoelke@arm.com>
Wed, 4 Jun 2014 20:10:52 +0000 (21:10 +0100)
committerAndrew Thoelke <andrew.thoelke@arm.com>
Mon, 23 Jun 2014 13:55:44 +0000 (14:55 +0100)
commit167a935733a6e3e412b8ed6a60034d0d84895f2e
treec443557e8fe8ff50628567aa6ebfc11f6fc9f6dd
parent5298f2cb98b9bdc18eb2f25cd28180ba7fd000d8
Initialise CPU contexts from entry_point_info

Consolidate all BL3-1 CPU context initialization for cold boot, PSCI
and SPDs into two functions:
*  The first uses entry_point_info to initialize the relevant
   cpu_context for first entry into a lower exception level on a CPU
*  The second populates the EL1 and EL2 system registers as needed
   from the cpu_context to ensure correct entry into the lower EL

This patch alters the way that BL3-1 determines which exception level
is used when first entering EL1 or EL2 during cold boot - this is now
fully determined by the SPSR value in the entry_point_info for BL3-3,
as set up by the platform code in BL2 (or otherwise provided to BL3-1).

In the situation that EL1 (or svc mode) is selected for a processor
that supports EL2, the context management code will now configure all
essential EL2 register state to ensure correct execution of EL1. This
allows the platform code to run non-secure EL1 payloads directly
without requiring a small EL2 stub or OS loader.

Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
17 files changed:
bl1/aarch64/bl1_arch_setup.c
bl31/aarch64/bl31_arch_setup.c
bl31/aarch64/context.S
bl31/bl31_main.c
bl31/context_mgmt.c
include/bl31/context_mgmt.h
include/common/bl_common.h
include/lib/aarch64/arch.h
include/lib/aarch64/arch_helpers.h
services/spd/tspd/tspd_common.c
services/spd/tspd/tspd_main.c
services/std_svc/psci/psci_afflvl_off.c
services/std_svc/psci/psci_afflvl_on.c
services/std_svc/psci/psci_afflvl_suspend.c
services/std_svc/psci/psci_common.c
services/std_svc/psci/psci_private.h
services/std_svc/psci/psci_setup.c