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(parent: 607dfdf) | patch
MX53: DDR: Fix ZQHWCTRL field TZQ_CS
authorTroy Kisky <troy.kisky@boundarydevices.com>
Thu, 22 Mar 2012 12:00:31 +0000 (12:00 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 16 Apr 2012 12:53:58 +0000 (14:53 +0200)
commit148241053123f3c2388d755807438fbe44dd2139
tree9fe038dbbe9cec28b1f9e6af030d9ee719eb2ac6tree | snapshot
parent607dfdf568baa506dc4ff33a38be3478820648fdcommit | diff
MX53: DDR: Fix ZQHWCTRL field TZQ_CS

Currently, board files are setting this field to 0x01
which the manual says is a reserved value. Change to
use the default of 0x02 - 128 cycles.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
board/freescale/mx53ard/imximage_dd3.cfg diff | blob | history
board/freescale/mx53evk/imximage.cfg diff | blob | history
board/freescale/mx53loco/imximage.cfg diff | blob | history
board/freescale/mx53smd/imximage.cfg diff | blob | history
Broadcom-s U-Boot