arm64: Add workaround for Cavium erratum 27456
authorAndrew Pinski <apinski@cavium.com>
Thu, 25 Feb 2016 01:44:57 +0000 (17:44 -0800)
committerCatalin Marinas <catalin.marinas@arm.com>
Fri, 26 Feb 2016 15:14:27 +0000 (15:14 +0000)
commit104a0c02e8b1936c049e18a6d4e4ab040fb61213
tree405d1e134395cca369a63f3580f7f98a326c406e
parent2f39b5f91eb4bccd786d194e70db1dccad784755
arm64: Add workaround for Cavium erratum 27456

On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
instructions may cause the icache to become corrupted if it contains
data for a non-current ASID.

This patch implements the workaround (which invalidates the local
icache when switching the mm) by using code patching.

Signed-off-by: Andrew Pinski <apinski@cavium.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Documentation/arm64/silicon-errata.txt
arch/arm64/Kconfig
arch/arm64/include/asm/cpufeature.h
arch/arm64/kernel/cpu_errata.c
arch/arm64/mm/proc.S