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pinctrl: tegra: Renumber the GG.0 and GG.1 pins
authorThierry Reding <treding@nvidia.com>
Thu, 19 Mar 2020 12:27:36 +0000 (13:27 +0100)
committerLinus Walleij <linus.walleij@linaro.org>
Fri, 27 Mar 2020 10:44:59 +0000 (11:44 +0100)
commit103afc8e9e8c4eff96052b311d19f7c32b653ebb
treeb201003c0a231cff3afa2b7a14fc93bdfcd965c6tree | snapshot
parentf67499f8ea7c15818d3375d718bd6cde4ae3d4f5commit | diff
pinctrl: tegra: Renumber the GG.0 and GG.1 pins

There is no need to define these at a specific offset since they are the
only pins defined for this SoC generation. Begin numbering them at 0.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20200319122737.3063291-9-thierry.reding@gmail.com
Tested-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drivers/pinctrl/tegra/pinctrl-tegra194.c diff | blob | history
John Crispins staging tree