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(parent: e4a6376) | patch
regulator: max8649 - fix setting extclk_freq
authorAxel Lin <axel.lin@gmail.com>
Fri, 1 Oct 2010 05:56:27 +0000 (13:56 +0800)
committerLiam Girdwood <lrg@slimlogic.co.uk>
Sat, 2 Oct 2010 13:19:45 +0000 (14:19 +0100)
commit0f69c897f378bf975c519b1d2455c03d06477dfa
tree18724ed7024cd3e2b7b45826a1091aea50664bf3tree | snapshot
parente4a6376b3b2999d169b602a582a8819d95ff79bccommit | diff
regulator: max8649 - fix setting extclk_freq

The SYNC bits are BIT6 and BIT7 of MAX8649_SYNC register.
pdata->extclk_freq could be [0|1|2].
(MAX8649_EXTCLK_26MHZ|MAX8649_EXTCLK_13MHZ|MAX8649_EXTCLK_19MHZ)
It requires to left shift 6 bits to properly set extclk_freq.

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
drivers/regulator/max8649.c diff | blob | history
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