riscv: Add a SYSCON driver for Andestech's PLIC
authorRick Chen <rick@andestech.com>
Tue, 2 Apr 2019 07:56:39 +0000 (15:56 +0800)
committerAndes <uboot@andestech.com>
Mon, 8 Apr 2019 01:45:08 +0000 (09:45 +0800)
commit0d389468e2144f3ba3bdbc566c05c0c05dc14fc6
treeb48b25b552a66db5d7e92dd23bdacf82484ddd41
parentd0a8fd3e4d2a5ab19b8f2d27d40dacb4942ba5a4
riscv: Add a SYSCON driver for Andestech's PLIC

The Platform-Level Interrupt Controller (PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt. It is required
for handling IPI.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
arch/riscv/Kconfig
arch/riscv/include/asm/global_data.h
arch/riscv/include/asm/syscon.h
arch/riscv/lib/Makefile
arch/riscv/lib/andes_plic.c [new file with mode: 0644]